TrueSilicon- High-Performance Scalable Silicon IP Solutions for Next-Generation Designs

OVERVIEW

The AXI2CHI bridge is a high-performance protocol converter that enables seamless integration between AXI (Advanced eXtensible Interface) and CHI (Coherent Hub Interface) domains. It enables AXIbased components to access and interact with a CHI-based coherent interconnect.

The bridge converts AXI channel-based transactions into CHI request, response, and data messages while preserving transaction semantics, data integrity, and ordering requirements. AXI burst transfers are translated into CHI multi-beat data transfers, and transaction attributes such as ID, transfer size, and byte strobes are mapped into their CHI equivalents.

To support high concurrency, the design tracks outstanding transactions and manages multiple in-flight operations efficiently. It enforces AXI ordering rules while adapting them to CHI's transaction model. Internal buffering and flow control logic bridge AXI's valid/ready handshake with CHI's credit-based and backpressure mechanisms, ensuring efficient data movement with low latency.

The AXI2CHI bridge also enables coherency support by translating AXI cacheable transactions into appropriate CHI coherent request types and handling snoop interactions within the CHI fabric. This allows AXI masters to participate in a coherent system without native CHI support.

Additionally, the bridge supports clock domain crossing (CDC) and reset domain management, enabling flexible deployment across multiple clock and reset domains.

Overall, the AXI2CHI bridge provides a scalable, configurable, and efficient solution for connecting AXI-based components to CHI-based coherent interconnects in modern SoC designs.

Key Highlights

Converts AXI channel-based transactions into CHI request (AW, W, AR → Req/Dat) and response (R, B → Rsp/Dat) messages
Translates AXI burst transactions into CHI multi-beat data transfers
Maps AXI beat count, data width, and write strobes into CHI transfer size and byte-enable fields
Maps AXI ID to CHI transaction ID/source ID
Tracks transaction IDs and enforces AXI ordering rules across CHI transactions
Supports data width conversion with upsizing/downsizing and beat packing/unpacking between AXI and CHI
Maps CHI error responses into AXI response codes (SLVERR, DECERR)
Buffers requests and responses and manages CHI credit-based / backpressure flow control
Maintains outstanding transaction tracking for multiple in-flight operations across AXI and CHI
Supports coherency by translating AXI cacheable transactions into appropriate CHI coherent request types and handling snoop interactions
Supports optional clock domain crossing (CDC) using asynchronous FIFOs between AXI and CHI domains
Provides reset domain synchronization or isolation between AXI and CHI interfaces

OVERVIEW

Additionally, the bridge supports clock domain crossing (CDC) and reset domain management, enabling flexible deployment across multiple clock and reset domains.

Overall, the AXI2CHI bridge provides a scalable, configurable, and efficient solution for connecting AXI-based components to CHI-based coherent interconnects in modern SoC designs.